Method and apparatus for allocating computing resources of processor based on processor load, and terminal

ABSTRACT

A method for allocating computing resources of a processor is provided. The method includes the follows. A current processor load is detected. Required computing resources are determined according to the current processor load. The required computing resources correspond to a total frequency of each processor core. Priori power values of each processor core at different frequencies are obtained. The number of processor cores and a frequency of each processor core are determined according to the priori power values of each processor core at different frequencies, such that a total frequency of each processor core satisfies the computing resources and a total power value of each processor core is minimum.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of International ApplicationPCT/CN2017/086447, filed on May 27, 2017, which claims priority toChinese Patent Application No. 201610380703.0, filed on May 31, 2016,the contents of both of which are herein incorporated by reference intheir entireties.

TECHNICAL FIELD

The present disclosure relates to the field of terminals, andparticularly to a method and an apparatus for allocating computingresources of a processor, and a terminal.

BACKGROUND

With a continuous development of processor technology, multi-coretechnology has become an important direction for current processordevelopment. Compared with related single-core chips, the multi-coreprocessor technology improves system's performance greatly with multipleprocessing cores' mutual assistance when a frequency is kept constant.

SUMMARY

According to a first aspect of implementations of the presentdisclosure, there is provided a method for allocating computingresources of a processor. The method includes the follows.

A current processor load is detected. Required computing resources aredetermined according to the current processor load. The requiredcomputing resources correspond to a total frequency of each processorcore. Priori power values of each processor core at differentfrequencies are obtained. The number of processor cores and a frequencyof each processor core are determined according to the priori powervalues of each processor core at different frequencies, such that atotal frequency of each processor core satisfies the computing resourcesand a total power value of each processor core is minimum.

According to a second aspect of the implementations of the presentdisclosure, there is provided a terminal device, which includes at leastone processor and a computer readable storage coupled to the at leastone processor. The computer readable storage stores at least onecomputer executable instruction thereon, which when executed by the atleast one processor, cause the at least one processor to carry outactions, including: detecting a current processor load; determiningrequired computing resources according to the current processor load,the required computing resources corresponding to a total frequency ofeach processor core; obtaining priori power values of each processorcore at different frequencies; determining the number of processor coresand a frequency of each processor core according to the priori powervalues of each processor core at different frequencies, with a totalfrequency of each processor core satisfying the required computingresources and a total power value of each processor core being minimum.

According to a third aspect of the disclosure, there is provided anon-transitory computer-readable storage medium storing a computerprogram which, when executed by a processor, cause the processor tocarry out following actions: detecting a current processor load;determining required computing resources according to the currentprocessor load, the required computing resources corresponding to atotal frequency of each processor core; obtaining priori power values ofeach processor core at different frequencies; determining the number ofprocessor cores and a frequency of each processor core according to thepriori power values of each processor core at different frequencies,with a total frequency of each processor core satisfying the requiredcomputing resources and a total power value of each processor core beingminimum.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate technical solutions of implementations of thepresent disclosure more clearly, the drawings used in theimplementations will be briefly described below. It will be apparentthat the drawings described in the following are merely someimplementations of the present disclosure, and it will be apparent tothose skilled in the art that other drawings can be obtained from thedrawings without any creative work.

FIG. 1 is a schematic flow chart illustrating a method for allocatingcomputing resources of a processor according to an implementation of thepresent disclosure.

FIG. 2 is a schematic structural diagram illustrating an apparatus forallocating computing resources of a processor according to animplementation of the present disclosure.

FIG. 3 is a schematic structural diagram illustrating a computer devicefor executing the method for allocating computing resources of aprocessor according to an implementation of the present disclosure.

DETAILED DESCRIPTION

Technical solutions of the present disclosure will be described clearlyand completely with reference to the accompanying drawings; obviously,implementations described below are merely part of rather than all ofthe implementations of the present disclosure. Based on theimplementations of the present disclosure, other implementationsobtained there from without any creative work by those of ordinary skillin the art shall fall into the protection scope of the presentdisclosure.

It should be noted that, terms involved in the implementations of thepresent disclosure are only for the purpose of describing specificimplementations, and are not intended to limit the present disclosure.Singular forms “a”, “an”, and “the” involved in the implementations ofthe present disclosure and appended claims are intended to includeplural forms as well, unless a context clearly indicates other meanings.It should also be understood that, the term “and/or” involved hereinrefers to and includes any and all possible combinations of one or moreof associated listed items.

A method for allocating computing resources of a processor is providedin the implementations of the present disclosure. An implementation ofthe method can depend on computer programs, which can run in a computersystem based on a von Neumann system. The computer programs can beprocessor controlled application programs of a multi-core processor of aterminal. The computer system can be a terminal device where theabove-mentioned computer programs running, such as a smart phone, atablet personal computer, a personal computer, and the like.

The “terminal” involved in the implementations of the present disclosurecan include a smart phone, a tablet personal computer, a vehicleterminal, a computer, and the like.

The “processor load” involved in the implementations of the presentdisclosure can refer to the number of processes that are currentlyprocessed and the number of processes to be processed by the processor.

The “computing resources” involved in the implementations of the presentdisclosure can refer to operating frequencies corresponding to processorcores.

The “foreground user operation” is relative to background useroperation. The foreground user operation is for foreground applications.The foreground applications refer to applications which are operatedcurrently. The background user applications refer to applications whichare not operated currently but still running in background.

In practice, those skilled in the art find that an actual load of aprocessor is different in different application scenarios. For example,there may be a large load difference between different foregroundapplications. For example, playing music requires a very lightweightload, taking photos or web browsing requires a moderate load,large-scale games require a heavy load, and there is a large differencein the required number and frequency resources of central processingunits (CPUs) or graphics processing units (GPUs). In addition, a largenumber of background applications are also running in the terminal,which also requires a certain amount of processor resources. Inprocessor core control of an operating system, a frequency governor isresponsible for frequency hopping and voltage regulation of a kernel,and a hot-plug control unit is responsible for switching of a pluralityof processor cores. The frequency governor is usually a function modulethat runs periodically to predict a subsequent load based on a currentoperating frequency, load, and a direction of change of the processorload of currently running CPU/GPU. The frequency governor can determinean operating frequency of the CPU/GPU in a next cycle, to dynamicallyadjust the CPU/GPU operating frequency in real time. The processingmethod is mainly to preset load periodically based on current operatingfrequency and direction of change of the processor load (the “directionof change of the processor load” means the processor load is increasingor decreasing), or determine switching of each processor core accordingto the number of tasks running per unit time. That is, it is difficultfor the frequency governor and the hot-plug control unit to distinguishdifferent load requirements of foreground and background applications,and cannot control allocation of processor resources based on loadsaccurately.

That is to say, in control schemes of a multi-core processor in therelated art, the processor cannot distinguish different loadrequirements of foreground and background applications, and cannotcontrol the allocation of processor resources based on the loadaccurately. This can lead to the following problems, for example,processor overload, a phenomenon such as a stuck caused by insufficientprocessing ability of the processor, or some processor cores may run ina “idle” state due to processor under-load, which in turn leads tounnecessary power waste.

According to a first aspect of implementations of the presentdisclosure, there is provided a method for allocating computingresources of a processor. The method includes: detecting a currentprocessor load; determining required computing resources according tothe current processor load, the required computing resourcescorresponding to a total frequency of each processor core; obtainingpriori power values of each processor core at different frequencies;determining the number of processor cores and a frequency of eachprocessor core according to the priori power values of each processorcore at different frequencies, with a total frequency of each processorcore satisfying the required computing resources and a total power valueof each processor core being minimum.

In an implementation, the detecting a current processor load includes:obtaining a processor load of each processor core in a current state;determining the current processor load according to the processor loadof each processor core in the current state.

In an implementation, the obtaining priori power values of eachprocessor core at different frequencies includes: determining acorrespondence between operating frequencies and power values of eachprocessor core, the power values being exponentially related to theoperating frequencies; determining the power values of each processorcore at different frequencies according to the correspondence.

In an implementation, the method further includes the follows after thedetecting a current processor load: determining the minimum number ofrequired processor cores according to the current processor load;determining the maximum number of processor cores in a system;determining a selectable range of the number of processor coresaccording to the minimum number and the maximum number of processorcores; determining a plurality of frequency allocation strategiesaccording to a formula N_(c_x)*F_(x)=N_(c_min)*F_(max); the value ofN_(c_x) being in [N_(c_min), N_(c_max)], N_(c_min) referring to theminimum number of required processor cores, N_(c_max) referring to themaximum number of processor cores in the system, F_(max) referring tothe maximum frequency of a single processor core, and F_(x) referring toa frequency allocated to a processor core; the determining the number ofprocessor cores and a frequency of each processor core according to thepriori power values of each processor core at different frequenciesincludes: determining a frequency allocation strategy according to thepriori power values of each processor core at different frequencies,with the total power value of each processor core corresponding to thefrequency allocation strategy determined being minimum.

In an implementation, the determining the minimum number of requiredprocessor cores according to the current processor load includes:determining the minimum number of required processor cores according toa formula N_(c_min)=[(L_(c)+100)/100], L_(c) referring to the currentprocessor load.

In an implementation, the method further includes the follows after thedetecting a current processor load: setting the current processor loadto a single processor core, when the minimum number of requiredprocessor cores determined according to the current processor load isone and there is no foreground user operation.

In an implementation, the method further includes the follows after thedetermining the number of processor cores and a frequency of eachprocessor core according to the priori power values of each processorcore at different frequencies: applying configurations of the number ofprocessor cores and the frequency of each processor core to theprocessor cores by calling interfaces of a frequency governor and ahot-plug unit.

In an implementation, the processor cores include a central processingunit (CPU) core and a graphics processing unit (GPU) core.

According to a second aspect of the implementations of the presentdisclosure, there is provided a terminal device which includes at leastone processor and a computer readable storage coupled to the at leastone processor. The computer readable storage stores at least onecomputer executable instruction thereon, which when executed by the atleast one processor, cause the at least one processor to carry outactions, including: detecting a current processor load; determiningrequired computing resources according to the current processor load,the required computing resources corresponding to a total frequency ofeach processor core; obtaining priori power values of each processorcore at different frequencies; determining the number of processor coresand a frequency of each processor core according to the priori powervalues of each processor core at different frequencies, with a totalfrequency of each processor core satisfying the required computingresources and a total power value of each processor core being minimum.

In an implementation, the at least one processor carrying out the actionof detecting the current processor load is caused to carry out actions,including: obtaining a processor load of each processor core in acurrent state; determining the current processor load according to theprocessor load of each processor core in the current state.

In an implementation, the at least one processor carrying out the actionof obtaining priori power values of each processor core at differentfrequencies, including: determining a correspondence between operatingfrequencies and power values of each processor core, the power valuesbeing exponentially related to the operating frequencies; determiningthe power values of each processor core at different frequenciesaccording to the correspondence.

In an implementation, the at least one processor is further caused tocarry out actions, including: determining the minimum number of requiredprocessor cores according to the current processor load; determining themaximum number of processor cores in a system; determining a selectablerange of the number of processor cores according to the minimum numberand the maximum number of processor cores; determining a plurality offrequency allocation strategies according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max); the value of N_(c_x) being in[N_(c_min), N_(c_max)], N_(c_min) referring to the minimum number ofrequired processor cores, N_(c_max) referring to the maximum number ofprocessor cores in the system, F_(max) referring to the maximumfrequency of a single processor core, and F_(x) referring to a frequencyallocated to a processor core; the at least one processor carrying outthe action of determining the number of processor cores and thefrequency of each processor core according to the priori power value ofeach processor core at different frequencies is caused to carry outactions, including: determining a frequency allocation strategyaccording to the priori power values of each processor core at differentfrequencies, with the total power value of each processor corecorresponding to the frequency allocation strategy determined beingminimum.

In an implementation, the at least one processor carrying out the actionof determining the minimum number of required processor cores accordingto the current processor load is caused to carry out actions, including:determining the minimum number of required processor cores according toa formula N_(c_min)=[(L_(c)+100)/100], L_(c) referring to the currentprocessor load.

In an implementation, the at least one processor is further caused tocarry out actions, including: setting the current processor load to asingle processor core, when the minimum number of required processorcores determined according to the current processor load is one andthere is no foreground user operation.

In an implementation, the at least one processor is further caused tocarry out actions, including: applying configurations of the number ofprocessor cores and the frequency of each processor core to theprocessor cores by calling interfaces of a frequency governor and ahot-plug unit.

In an implementation, the processor cores comprise a central processingunit (CPU) core and a graphics processing unit (GPU) core.

According to a third aspect of the implementations of the presentdisclosure, there is provided a non-transitory computer-readable storagemedium storing a computer program which, when executed by a processor,causes the processor to carry out actions: detecting a current processorload; determining required computing resources according to the currentprocessor load, the required computing resources corresponding to atotal frequency of each processor core; obtaining priori power values ofeach processor core at different frequencies; determining the number ofprocessor cores and a frequency of each processor core according to thepriori power values of each processor core at different frequencies,with a total frequency of each processor core satisfying the requiredcomputing resources and a total power value of each processor core beingminimum.

In an implementation, the computer program executed by the processor tocarry out the action of detecting the current processor load is executedby the processor to carry out actions, including: obtaining a processorload of each processor core in a current state; determining the currentprocessor load according to the processor load of each processor core inthe current state.

In an implementation, the computer program executed by the processor tocarry out the action of obtaining the priori power values of eachprocessor core at different frequencies is executed by the processor tocarry out actions, including: determining a correspondence betweenoperating frequencies and power values of each processor core, the powervalues being exponentially related to the operating frequencies;determining the power values of each processor core at differentfrequencies according to the correspondence.

In an implementation, the computer program is further executed by theprocessor to carry out actions: determining the minimum number ofrequired processor cores according to the current processor load;determining the maximum number of processor cores in a system;determining a selectable range of the number of processor coresaccording to the minimum number and the maximum number of processorcores; determining a plurality of frequency allocation strategiesaccording to a formula N_(c_x)*F_(x)=N_(c_min)*F_(max); the value ofN_(c_x) being in [N_(c_min), N_(c_max)], N_(c_min) referring to theminimum number of required processor cores, N_(c_max) referring to themaximum number of processor cores in the system, F_(max) referring tothe maximum frequency of a single processor core, and F_(x) referring toa frequency allocated to a processor core; the computer program executedby the processor to carry out the action of obtaining the priori powervalues of each processor core at different frequencies is executed bythe processor to carry out actions, including: determining a frequencyallocation strategy according to the priori power values of eachprocessor core at different frequencies, with the total power value ofeach processor core corresponding to the frequency allocation strategydetermined being minimum.

By means of the method and the apparatus for allocating computingresources of a processor, and the terminal, the number and frequenciesof operating processor cores are optimized in a range of processorresources allowed by a system according to a current processor loadcondition of the terminal and minimum computing resources currentlyrequired. That is, according to different power consumption parameterscorresponding to different combinations of the number and thefrequencies of processor cores, an optimal power consumption result canbe obtained under the premise that a performance requirement is met.That is, the number and the frequencies of operating processors coresare determined. By means of the method and the apparatus for allocatingcomputing resources of a processor, the power consumption of theterminal can be reduced under the premise of ensuring performance of adisplay thread.

In order to reduce unnecessary power consumption of the processor, asillustrated in FIG. 1, the method for allocating computing resources ofa processor can include operations at blocks 102 to 108.

At block 102, a current processor load(s) is detected.

In implementations of the present disclosure, the processor involved canbe a central processing unit (CPU), a graphics processing unit (GPU), amicro controller unit (MCU), or any combination thereof. Moreover, theprocessor involved in the implementations can be a symmetricalmulti-core processor or an asymmetric multi-core processor.

The processor load depends on the number of processes that are currentlyprocessed and the number of processes to be processed by the processor.Generally speaking, the larger the load, the more processing resourcesare occupied in the processor, that is, the smaller remaining processingability. In this implementation, for a plurality of cores of theprocessor in the terminal, a processor load of each processor core in acurrent state is obtained respectively.

At block 104, required computing resources are determined according tothe current processor load. The required “computing resources”correspond to a total frequency of each operating processor core.

The computing resources refer to operating frequencies corresponding toprocessor cores. Threshold computing resources of a processor core canrepresent the largest operating frequency at which the processor coreoperates. In order to support the current processor load, that is, thenumber of processes and task amount that are processed currently and tobe processed by the processor, the operating frequencies of theprocessor cores need to be ensured.

In this implementation of the present disclosure, an operating frequencycorresponding to each processor load can be determined correspondingly,and then the total operating frequency corresponding to a totalprocessor load can be calculated. The total operating frequency canrefer to a sum of operating frequencies of the processor cores withprocessor loads. The total operating frequency can refer to computingresources required by all processor loads (in other words, the totalprocessor load), that is, computing resources required to be allocatedto the terminal by the processor cores for processing current process ortasks of the terminal.

At block 106, priori power values of each processor core at differentfrequencies are obtained, the number of processor cores and a frequencyof each processor core are determined according to the priori powervalues, with a total frequency of each processor core satisfying therequired computing resources and a total power value of each processorcore being minimum.

In the implementations, power values of each processor core at differentoperating frequencies need to be obtained in advance, that is, acorrespondence between operating frequencies and power values of eachprocessor core needs to be determined. Herein, the “each processor core”can be any one processor core of the processor. In this implementation,the correspondence can be provided by processor manufactures, or can beexperimental results obtained by the terminal in advance. Generallyspeaking, the operating frequency of the processor core is notproportional to the power value; instead, the operating frequency isexponentially related to the power value. That is, the power valueincreases exponentially with the increase of the operating frequency.

After obtaining the correspondence between operating frequencies andpower values of each processor core, the number of processor cores andthe frequency of each operating processor core can be determinedaccording to the correspondence. For example, we suppose computingresources corresponding to a processor load is 4G, the number ofavailable processor cores is four, and the maximum calculation amount ofeach processor core is 4G, then for the above-identified requirement of4G computing resources, four kinds of combinations of processor coresare listed in the following.

1. A single processor core operates at an operating frequency of 4G.

2. Two processor cores operate at an operating frequency of 2Grespectively.

3. Three processor cores operate at an operating frequency of 4/3Grespectively.

4. Four processor cores operate at an operating frequency of 1Grespectively.

All of the above-mentioned four kinds of combinations of the operatingnumber and operating frequency of processor cores can satisfy thecurrent load of the terminal, that is, an overall processing ability ofthe processor is sufficient. As for the above-mentioned variouscombination mode, which one is selected depends on a specific powerconsumption of a combination. The total power value of each processorcore of the combination mode selected will be minimum. That is, thenumber and the operating frequencies of processor cores selected arecapable of resulting a minimum a power consumption of the processor.

It should be noted that, in this implementation, the operating frequencyof each processor core selected can be same or different from eachother.

For example, for the above-identified requirement of 4G computingresources, there are also various combinations of processor cores listedin the following, where the operating frequency of each processor coreselected is different from each other.

1. There can be two processor cores selected, one processor coreoperates at an operating frequency of 1G, and the other operates at anoperating frequency of 3G.

2. There can be three processor cores selected, the first and secondprocessor core operates at an operating frequency of 1G, and the thirdoperates at an operating frequency of 2G respectively.

There are also many combinations of processor cores, which is notlimited herein.

After the current processor load is detected, the following operationscan be conducted. The minimum number of required processor cores isdetermined according to the current processor load. The maximum numberof processor cores in a system is determined. A selectable range of thenumber of processor cores is determined according to the minimum numberand the maximum number of processor cores. A plurality of frequencyallocation strategies is determined according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max).

The value of N_(c_x) is in [N_(c_min), N_(c_max)] ([N_(c_min),N_(c_max)] means integers from N_(c_min) to N_(c_max), includingN_(c_min) and N_(c_max)), N_(c_min) refers to the minimum number ofrequired processor cores, N_(c_max) refers to the maximum number ofprocessor cores in the system, F_(max) refers to the maximum frequencyof a single processor core, and F_(x) refers to a frequency allocated toa processor core.

For the formula N_(c_x)*F_(x)=N_(c_min) max, the operating frequency ofeach processor core selected can be same.

The number of processor cores and the frequency of each processor corecan be determined according to the priori power values of each processorcore at different frequencies as follows. A frequency allocationstrategy is determined according to the priori power values of eachprocessor core at different frequencies, where the total power value ofeach processor core corresponding to the frequency allocation strategydetermined is minimum.

L_(c) refers to the current processor load and the minimum number ofrequired processor cores corresponding to the load can be determinedwith the following formula: N_(c_min)=[(L_(c)+100)/100].

For example, when L_(c)=20% (that means twenty percent of the processingresources of the processor is occupied, or the remaining processingability of the processor is 80%), the minimum number of requiredprocessor cores is one; when L_(c)=120%, the minimum number of requiredprocessor cores is two.

The total number of processor cores in the terminal refers to themaximum number of allowable or available processor cores in theterminal, which is represented by N_(c_max) in this implementation. Forexample, as for a CPU with four cores, N_(c_max)=4; as for a CPU witheight cores, N_(c_max)=8.

The number of processor cores that can be selected for operation can bedetermined according to the minimum number N_(c_min) of requiredprocessor cores and the maximum number N_(c_max) of processor cores inthe system. For example, when N_(c_min)=1 and N_(c_max)=8, the numberN_(c_x) of processor cores that can be selected for operation can be 1,2, 3, 4, 5, 6, 7, and 8, which are integers in the range [1, 8]. Thevalue of N_(c_x) ranges from N_(c_min) to N_(c_max) (that is,[N_(c_min), N_(c_max])).

N_(c_min) can be determined according to the specific value of computingresources calculated via the operations at block 104 and the largestfrequency corresponding to each processor core. Various frequencyallocation strategies can be determined according to the formulaN_(c_x)*F_(x)=N_(c_min)*F_(max). F_(max) refers to the maximum frequencyof a single processor core and F_(x) refers to a frequency allocated toa processor core. Different combinations of numbers and operatingfrequencies of the processor cores can be determined based on the valuesof N_(c_x) and F_(x).

In the process of determining the number of processor cores and thefrequency of each processor core according to the priori power values ofeach processor core at different frequencies, a frequency allocationstrategy that satisfies the above-mentioned computing resources can bedetermined according to the priori power values of each processor coreat different frequencies, that is, according to a correspondence betweendifferent operating frequencies and power values of each processor core.In other words, a total operating frequency allocated to the processorcores satisfies the specific value of the computing resources obtainedvia the operations at block 104. Based on this, a frequency allocationstrategy with a minimum total power value will be selected. For example,a total power value under each frequency allocation strategy can becalculated, the minimum value of total power values can be determinedaccording to the calculated total power values, and a frequencyallocation strategy corresponding to the minimum value is selected. Thenumber and frequency of running processor cores of the frequencyallocation strategy thus obtained can be a frequency allocation strategywith the lowest power consumption level under the premise of satisfyingthe current load requirement of the system.

In another implementation, the method can further include the followsafter the current processor load is detected. The current processor loadis set to a single processor core, when the minimum number of requiredprocessor cores determined according to the current processor load isone and there is no foreground user operation.

In general, standby current in a single-core processor mode are lessthan that in a dual-core or multi-core processor mode, so the terminalload can be set to a single processor core where circumstances permit.Specifically, when the determined N_(c_min)=1, it means that a singleprocessor core is sufficient to carry the current load. In addition,when a user does not perform any foreground operation at present, itindicates that the user does not have a large load requirement on theterminal, therefore, the entire current processor load can be carriedout by a single processor, that is, the terminal can be turned into asingle processor core mode. For example, when the processor is a CPU,the terminal entered a single CPU core mode. By means of theimplementation, the standby current of the terminal can be significantlyreduced.

In this implementation, the number and the frequencies of operatingprocessor cores in the processor are determined according to theforegoing operations, and then the terminal needs to set the processorthereof according to the determined number and frequencies of operatingprocessor cores in the processor. In this implementation, in processorcore control of an operating system, a frequency governor is responsiblefor frequency hopping and voltage regulation of a kernel, and a CPU/GPUhot-plug control unit is responsible for switching of a plurality ofprocessing cores. That is, switching of the processor cores andfrequency adjustment are completed through the frequency governor andthe hot-plug control unit. In an implementation, the method can furtherinclude the follows after the number of processor cores and thefrequency of each processor core are determined according to the prioripower values of each processor core at different frequencies.Configurations of the number of processor cores and the frequency ofeach processor core are applied to processor cores by calling interfacesof the frequency governor and the hot-plug unit.

In one implementation, as illustrated in FIG. 2, an apparatus forallocating computing resources of a processor is also provided. Theapparatus for allocating computing resources of a processor includes adetecting unit 102, a calculating unit 104, and a combinationdetermining unit 106.

The detecting unit 102 is configured to detect a current processor load.

In implementations of the present disclosure, the processor involved canbe a central processing unit (CPU), a graphics processing unit (GPU), amicro controller unit (MCU), or any combination thereof. Moreover, theprocessor involved in the implementations can be a symmetricalmulti-core processor or an asymmetric multi-core processor.

The processor load depends on the number of processes that are currentlyprocessed and the number of processes to be processed by the processor.Generally speaking, the larger the load, the more processing resourcesare occupied in the processor, that is, the smaller remaining processingability. In this implementation, for a plurality of cores of theprocessor in the terminal, the detecting unit 102 obtains a processorload of each processor core in a current state respectively.

The calculating unit 104 is configured to determine required computingresources according to the current processor load. The required“computing resources” correspond to a total frequency of each processorcore.

The computing resources refer to operating frequencies corresponding toprocessor cores, Threshold computing resources of a processor core canrepresent the largest operating frequency at which the processor coreoperates. In order to support the current processor load, that is, thenumber of processes and task amount that are processed currently and tobe processed by the processor, the operating frequencies of theprocessor cores need to be ensured.

In the implementations of the present disclosure, the calculating unit104 determines an operating frequency corresponding to each processorload correspondingly, and then calculate a total operating frequencycorresponding to a total processor load. The total operating frequencycan refer to computing resources required by all processor loads (inother words, the total processor load), that is, computing resourcesrequired to be allocated to the terminal by the processor cores forprocessing current process or tasks of the terminal.

The combination determining unit 106 is configured to determine thenumber of processor cores and a frequency of each processor coreaccording to the priori power values of each processor core at differentfrequencies, with a total frequency of each processor core conforms to(in other words, satisfying) the computing resources and a total powervalue of each processor core is minimum.

In the implementations, the combination determining unit 106 needs toobtain power values of each processor core at different operatingfrequencies in advance, that is, the combination determining unit 106determines a correspondence between operating frequencies and powervalues of each processor core. In this implementation, thecorrespondence can be provided by processor manufactures, or can beexperimental results obtained by the terminal in advance. Generallyspeaking, the operating frequency of the processor core is notproportional to the power value; instead, the operating frequency isexponentially related to the power value. That is, the power valueincreases exponentially with the increase of the operating frequency.

After obtaining the correspondence between operating frequencies andpower values of each processor, the combination determining unit 106 candetermine the number of processor cores and the frequency of eachprocessor core according to the correspondence. For example, we supposecomputing resources corresponding to a processor load is 4G, the numberof available processor cores is four, and the maximum calculation amountof each processor core is 4G, then for the above-identified requirementof 4G computing resources, four kinds of combinations of processor coresare listed in the following.

1. a single processor core operates at an operating frequency of 4G.

2. two processor cores operate at an operating frequency of 2Grespectively.

3. three processor cores operate at an operating frequency of 4/3Grespectively.

4. four processor cores operate at an operating frequency of 1Grespectively.

All of the above-mentioned four kinds of combinations of the operatingnumbers and operating frequencies of processor cores can satisfy thecurrent load of the terminal, that is, an overall processing ability ofthe processor is sufficient. As for the above-mentioned variouscombinations mode, which one is selected depends on a specific powerconsumption of a combination. The total power value of each processorcore of the combination mode selected will be minimum. That is, thenumber and the operating frequencies of processor cores selected arecapable of resulting a minimum power consumption of the processor.

It should be noted that, in this implementation, the operating frequencyof each processor core can be same or different from each other.

In an implementation, as illustrated in FIG. 2, the apparatus canfurther include a strategy determining unit 108. The strategydetermining unit 108 is configured to: determine the minimum number ofrequired processor cores according to the current processor load;determine the maximum number of processor cores in a system; determine aselectable range of the number of processor cores according to theminimum number and the maximum number of processor cores; determine aplurality of frequency allocation strategies according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max). The value of N_(c_x) is in [N_(c_min),N_(c_max)] ([N_(c_min), N_(c_max)] means integers from N_(c_min) toN_(c_max), including N_(c_min) and N_(c_max)), N_(c_min) refers to theminimum number of required processor cores, N_(c_max) refers to themaximum number of processor cores in the system, F_(max) refers to themaximum frequency of a single processor core, and F_(x) refers to afrequency allocated to a processor core.

The combination determining unit 106 is configured to determine afrequency allocation strategy according to the priori power values ofeach processor core at different frequencies. The total power value ofeach processor core corresponding to the frequency allocation strategydetermined is minimum.

L_(c) refers to the current processor load and the minimum number ofrequired processor cores corresponding to the load can be determinedwith the following formula: N_(c_min)=[(L_(c)+100)/100].

For example, when L_(c)=20%, the minimum number of required processorcores is one; when L_(c)=120%, the minimum number of required processorcores is two.

The total number of processor cores in the terminal refers to themaximum number of allowable or available processor cores in theterminal, which is represented by N_(c_max) in this implementation. Forexample, as for a CPU with four cores, N_(c_max) four; as for a CPU witheight cores, N_(c_max)=eight.

The strategy determining unit 108 can determine the number of processorcores which can be selected for operation according to the minimumnumber N_(c_min) of required processor cores and the maximum numberN_(c_max) of processor cores in the system. For example, whenN_(c_min)=1 and N_(c_max)=8, the number N_(c_x) of processor cores whichcan be selected for operation can be 1, 2, 3, 4, 5, 6, 7, and 8, whichare integers in the range [1, 8]. The value of N_(c_x) ranges fromN_(c_min) to N_(c_max) (that is, [N_(c_min), N_(c_max])).

The strategy determining unit 108 can determine N_(c_min) according tothe specific value of computing resources calculated by the calculatingunit 104 and the largest frequency corresponding to each processor core.Various frequency allocation strategies can be determined according tothe formula N_(c_x)*F_(x)=N_(c_min)*F_(max). F_(max) refers to themaximum frequency of a single processor core and F_(x) refers to afrequency allocated to a processor core. Different combinations ofnumbers and operating frequencies of the processor cores can bedetermined based on the values of N_(c_x) and F_(x).

In the process of the strategy determining unit 108 determining thenumber of processor cores and the frequency of each processor coreaccording to the priori power values of each processor core at differentfrequencies, a frequency allocation strategy that satisfies theabove-mentioned computing resources can be determined according to thepriori power values of each processor core at different frequencies,that is, according to a correspondence between different operatingfrequencies and power values of each processor core. In other words, atotal operating frequency allocated to the processor cores satisfies thespecific value of the above obtained computing resources. Based on this,a frequency allocation strategy with a minimum total power value will beselected. For example, the strategy determining unit 108 can calculate atotal power value under each frequency allocation strategy, determinethe minimum value of total power values according to the calculatedtotal power values, and select a frequency allocation strategycorresponding to the minimum value. The number and the frequency ofoperating processor cores of the frequency allocation strategy thusobtained can be a frequency allocation strategy with the lowest powerconsumption level under the premise of satisfying the current loadrequirement of the system.

In another implementation, the apparatus can further include a settingunit 110. The setting unit 110 is configured to set the currentprocessor load to a single processor core, when the minimum number ofrequired processor cores determined according to the current processorload is one and there is no foreground user operation.

In general, standby current in a single-core processor mode are lessthan that in a dual-core or multi-core processor mode, so the settingunit 110 can set the terminal load to a single processor core wherecircumstances permit. Specifically, when the determined N_(c_min)=1, itmeans that a single processor core is sufficient to carry the currentload. In addition, when a user does not perform any foreground operationat present, it indicates that the user does not have a large loadrequirement on the terminal, therefore, the setting unit 110 can set theentire current processor load to a single processor to be carried out,that is, the terminal can be turned into a single processor core mode.For example, when the processor is a CPU, the terminal entered a singleCPU core mode. By means of the implementation, the standby current ofthe terminal can be significantly reduced.

In another implementation, as illustrated in FIG. 2, the apparatus canfurther include an applying unit 112. The applying unit 112 isconfigured to apply configurations of the number of processor cores andthe frequency of each processor core to processor cores by callinginterfaces of a frequency governor and a hot-plug unit.

In this implementation, the applying unit 112 needs to set the processorof the terminal according to the determined number and frequencies ofoperating processor cores in the processor. In this implementation, inprocessor core control of an operating system, a frequency governor isresponsible for frequency hopping and voltage regulation of a kernel,and a CPU/GPU hot-plug control unit is responsible for switching of aplurality of processing cores. That is, switching of the processor coresand frequency adjustment are completed through the frequency governorand the hot-plug control unit. In an implementation, the method canfurther include the follows after the number of processor cores and thefrequency of each processor core are determined according to the prioripower values of each processor core at different frequencies.Configurations of the number of processor cores and the frequency ofeach processor core are applied to processor cores by calling interfacesof the frequency governor and the hot-plug unit.

By means of the implementations of the present disclosure, there are thefollowing beneficial effects.

By means of the method and the apparatus for allocating computingresources of a processor, the number and frequencies of operatingprocessor cores are optimized in a range of processor resources allowedby a system according to a current processor load condition of theterminal and minimum computing resources currently required. That is,according to different power consumption parameters corresponding todifferent combinations of the number and the frequencies of processorcores, an optimal power consumption result can be obtained under thepremise that a performance requirement is met. That is, the number andthe frequencies of operating processors cores are determined. By meansof the method and the apparatus for allocating computing resources of aprocessor, the power consumption of the terminal can be reduced underthe premise of ensuring performance of a display thread.

The above units can be realized through one or more processors, forexample, the above units can be integrated in one processor, or, can bedistributed among different processors.

In one implementation, as illustrated in FIG. 3, FIG. 3 illustrates aterminal based on a von Neumann system computer system that executes theabove-described method for allocating computing resources of aprocessor. The computer system can be a terminal device such as a smartphone, a tablet computer, a palm computer, a laptop computer, or apersonal computer. Specifically, the terminal can include an externalinput interface 1001, a processor 1002, a memory 1003, and an outputinterface 1004. The external input interface 1001, the processor 1002,the memory 1003, and the output interface 1004 can be connected througha system bus. In one implementation, the external input interface 1001can include at least a network interface 10012. The memory 1003 caninclude an external memory 10032 (such as a hard disk, an optical disk,or a floppy disk, etc.) and an internal memory 10034. The outputinterface 1004 can include at least a device such as a display screen10042.

In this implementation, the operation of the method is based on computerprograms. Program file of the computer programs is stored in theexternal memory 10032 of the aforementioned computer system based on thevon Neumann system, loaded into the internal memory 10034 when executed,and then passed to the processor 1002 for execution after being compiledinto machine code, so that a detecting unit 102, a calculating unit 104,and a combination determining unit 106 can be formed logically in thecomputer system based on the von Neumann system. In the executionprocess of the method for allocating computing resources of a processor,input parameters are all received through the external input interface1001, transferred to the memory 1003 to be buffered, and then input tothe processor 1002 to be processed. The processed result data can bebuffered in the memory 1003 for subsequent processing or can be passedto the output interface 1004 for output.

The implementations of the present disclosure also provide anon-transitory computer-readable storage medium. The non-transitorycomputer-readable storage medium stores computer programs which, whenexecuted by a processor, causes the processor to carry out all or partof the actions of any method for allocating computing resources of aprocessor based on a processor load described in the above-describedmethod implementations.

The implementations of the present disclosure also provide a computerprogram product. The computer program product includes a non-transitorycomputer readable storage medium for storing computer programs. Thecomputer programs, when executed, are operable with a computer toperform all or part of operations of any method according to the secondaspect of the implementations of the present disclosure. The computerprogram product can be a software installation package.

The above disclosed implementations are merely exemplary implementationsof the present disclosure and the scope of the present disclosure is notlimited thereto. Therefore, equivalent changes made according to theclaims of the present disclosure shall still fall within the scope ofthe present disclosure.

What is claimed is:
 1. A method for allocating computing resources of aprocessor based on a processor load, comprising: detecting a currentprocessor load; determining the minimum number of required processorcores according to the current processor load; determining the maximumnumber of processor cores in a system; determining a selectable range ofthe number of processor cores according to the minimum number and themaximum number of processor cores; determining a plurality of frequencyallocation strategies according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max), wherein the value of N_(c_x) is in[N_(c_min), N_(c_max)], N_(c_min) is the minimum number of requiredprocessor cores, N_(c_max) is the maximum number of processor cores inthe system, F_(max) is the maximum frequency of a single processor core,and F_(x) is a frequency allocated to a processor core; determiningrequired computing resources according to the current processor load,the required computing resources corresponding to a total frequency ofeach processor core; obtaining priori power values of each processorcore at different frequencies; determining the number of processor coresand a frequency of each processor core according to the priori powervalues of each processor core at different frequencies, with a totalfrequency of each processor core satisfying the required computingresources and a total power value of each processor core being minimum;and applying configurations of the number of processor cores and thefrequency of each processor core to the processor cores by callinginterfaces of a frequency governor and a hot-plug unit; wherein thedetermining the number of the processor cores and the frequency of eachprocessor core according to the priori power values of each processorcore at the different frequencies comprises: determining a frequencyallocation strategy according to the priori power values of eachprocessor core at different frequencies, with the total power value ofeach processor core corresponding to the frequency allocation strategydetermined being minimum.
 2. The method of claim 1, wherein detectingthe current processor load comprises: obtaining a processor load of eachprocessor core in a current state; and determining the current processorload according to the processor load of each processor core in thecurrent state.
 3. The method of claim 1, wherein obtaining the prioripower values of each processor core at the different frequenciescomprises: determining a correspondence between operating frequenciesand power values of each processor core, the power values beingexponentially related to the operating frequencies; and determining thepower values of each processor core at different frequencies accordingto the correspondence.
 4. The method of claim 1, wherein determining theminimum number of the required processor cores according to the currentprocessor load comprises: determining the minimum number of requiredprocessor cores according to a formula N_(c_min)=[(L_(c)+100)/100],wherein L_(c) is the current processor load.
 5. The method of claim 1,further comprising: after detecting the current processor load, settingthe current processor load to a single processor core, when the minimumnumber of required processor cores determined according to the currentprocessor load is one and there is no foreground user operation.
 6. Themethod of claim 1, wherein the processor cores comprise a centralprocessing unit (CPU) core and a graphics processing unit (GPU) core. 7.A terminal device, comprising: at least one processor; and a computerreadable storage, coupled to the at least one processor and storing atleast one computer executable instruction thereon, which when executedby the at least one processor, cause the at least one processor to:detect a current processor load; determine the minimum number ofrequired processor cores according to the current processor load;determine the maximum number of processor cores in a system; determine aselectable range of the number of processor cores according to theminimum number and the maximum number of processor cores; and determinea plurality of frequency allocation strategies according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max), wherein the value of N_(c_x) is in[N_(c_min), N_(c_max)], N_(c_min) is the minimum number of requiredprocessor cores, N_(c_max) is the maximum number of processor cores inthe system, F_(max) is the maximum frequency of a single processor core,and F_(x) is a frequency allocated to a processor core; determinerequired computing resources according to the current processor load,the required computing resources corresponding to a total frequency ofeach processor core; obtain priori power values of each processor coreat different frequencies; determine the number of processor cores and afrequency of each processor core according to the priori power values ofeach processor core at different frequencies, with a total frequency ofeach processor core satisfying the required computing resources and atotal power value of each processor core being minimum; applyconfigurations of the number of processor cores and the frequency ofeach processor core to the processor cores by calling interfaces of afrequency governor and a hot-plug unit; wherein the at least oneprocessor caused to determine the number of processor cores and thefrequency of each processor core according to the priori power value ofeach processor core at the different frequencies is further caused to:determine a frequency allocation strategy according to the priori powervalues of each processor core at different frequencies, with the totalpower value of each processor core corresponding to the frequencyallocation strategy determined being minimum.
 8. The terminal device ofclaim 7, the at least one processor to detect the current processor loadis further caused to: obtain a processor load of each processor core ina current state; and determine the current processor load according tothe processor load of each processor core in the current state.
 9. Theterminal device of claim 7, wherein the at least one processor to obtainthe priori power values of each processor core at the differentfrequencies is further caused to: determine a correspondence betweenoperating frequencies and power values of each processor core, the powervalues being exponentially related to the operating frequencies; anddetermine the power values of each processor core at differentfrequencies according to the correspondence.
 10. The terminal device ofclaim 7, wherein the at least one processor caused to determine theminimum number of required processor cores according to the currentprocessor load is further caused to: determine the minimum number ofrequired processor cores according to a formulaN_(c_min)=[(L_(c)+100)/100], wherein L_(c) is the current processorload.
 11. The terminal device of claim 7, wherein the at least oneprocessor is further caused to set the current processor load to asingle processor core, when the minimum number of required processorcores determined according to the current processor load is one andthere is no foreground user operation.
 12. The terminal device of any ofclaim 7, wherein the processor cores comprise a central processing unit(CPU) core and a graphics processing unit (GPU) core.
 13. Anon-transitory computer-readable storage medium storing a computerprogram which, when executed by a processor, causes the processor to:detect a current processor load; determine the minimum number ofrequired processor cores according to the current processor load;determine the maximum number of processor cores in a system; determine aselectable range of the number of processor cores according to theminimum number and the maximum number of processor cores; and determinea plurality of frequency allocation strategies according to a formulaN_(c_x)*F_(x)=N_(c_min)*F_(max), wherein the value of N_(c_x) is in[N_(c_min), N_(c_max)], N_(c_min) is the minimum number of requiredprocessor cores, N_(c_max) is the maximum number of processor cores inthe system, F_(max) is the maximum frequency of a single processor core,and F_(x) is a frequency allocated to a processor core; determinerequired computing resources according to the current processor load,computing resources corresponding to a total frequency of each processorcore; obtain priori power values of each processor core at differentfrequencies; determine the number of processor cores and a frequency ofeach processor core according to the priori power values of eachprocessor core at different frequencies, with a total frequency of eachprocessor core satisfying the required computing resources and a totalpower value of each processor core being minimum; apply configurationsof the number of processor cores and the frequency of each processorcore to the processor cores by calling interfaces of a frequencygovernor and a hot-plug unit; wherein the computer program executed bythe processor to obtain the priori power values of each processor coreat the different frequencies is executed by the processor to: determinea frequency allocation strategy according to the priori power values ofeach processor core at different frequencies, with the total power valueof each processor core corresponding to the frequency allocationstrategy determined being minimum.
 14. The non-transitorycomputer-readable storage medium of claim 13, wherein the computerprogram executed by the processor to detect the current processor loadis executed by the processor to: obtain a processor load of eachprocessor core in a current state; and determine the current processorload according to the processor load of each processor core in thecurrent state.
 15. The non-transitory computer-readable storage mediumof claim 13, wherein the computer program executed by the processor toobtain the priori power values of each processor core at the differentfrequencies is executed by the processor to: determine a correspondencebetween operating frequencies and power values of each processor core,the power values being exponentially related to the operatingfrequencies; and determine the power values of each processor core atdifferent frequencies according to the correspondence.
 16. Thenon-transitory computer-readable storage medium of claim 13, wherein thecomputer program is further executed by the processor to: determine theminimum number of required processor cores according to the currentprocessor load; determine the maximum number of processor cores in asystem; determine a selectable range of the number of processor coresaccording to the minimum number and the maximum number of processorcores; and determine a plurality of frequency allocation strategiesaccording to a formula N_(c_x)*F_(x)=N_(c_min)*F_(max), wherein thevalue of N_(c_x) is in [N_(c_min), N_(c_max)], N_(c_min) is the minimumnumber of required processor cores, N_(c_max) is the maximum number ofprocessor cores in the system, F_(max) is the maximum frequency of asingle processor core, and F_(x) is a frequency allocated to a processorcore; and wherein the computer program executed by the processor toobtain the priori power values of each processor core at the differentfrequencies is executed by the processor to: determine a frequencyallocation strategy according to the priori power values of eachprocessor core at different frequencies, with the total power value ofeach processor core corresponding to the frequency allocation strategydetermined being minimum.